Training
At SynVue, we believe that knowledge is the key to everything. Along with our impressive products development and networks, we also care for the possession of knowledge in the society. As we are aware of today's demand in this challenging world, we provide complete training courses mainly focusing on IC Design for every level of passionate learners.
Training Courses

Synthworks Courses


VHDL Coding for Synthesis

Course Overview

An in-depth study of VHDL RTL (FPGA and ASIC) coding styles, methodologies, design techniques, problem solving techniques, and advanced language constructs to produce better, faster, and smaller logic. 

Class topics focus on mapping digital hardware structures to vendor independent VHDL code. Detailed do's and don'ts of synthesis coding styles are discussed. Lecture and laboratory materials illustrate the optimization differences achieved by different VHDL coding styles. Students will learn proven coding practices that result in smaller and faster designs. The numerous examples in this course make it suitable for a student with limited VHDL. The application focus of this course results in the student being ready for VHDL based ASIC or FPGA design. 

Intended Audience

The numerous examples in this course make it suitable for a student with limited VHDL. The application focus of this course results in the student being ready for VHDL based ASIC or FPGA design. 

Available Class Formats

This class is available online, at public venues, or on-site (at your location). 

Course Objectives

Upon completion of this course, students will be able to:

  • Write efficient, vendor independent VHDL code
  • Use best coding styles and practices to create ASIC and FPGA logic
  • Understand and avoid problematic hardware coding styles
  • Use code templates to create a design from the block diagram
  • Read VHDL code and draw the corresponding hardware (reverse engineer)
  • Use types, overloading, and conversion functions from standard VHDL packages (std_logic_1164, numeric_std, and std_logic_arith)
  • Use advanced VHDL constructs to simplify the coding process
  • Identify and solve synthesis issues using VHDL coding techniques
  • Force a synthesis tool to create the desired logic structure

Course Outline

     Day 1, Module Syn1Synthesis OverviewCombinational LogicRegisters and LatchesUART Transmitter: RTL Code + Statemachine     Day 3, Module AdvSyn1Subprograms for SynthesisAdvanced Combinational LogicAdvanced Sequential LogicParameterizing Designs
     Day 2, Module Syn2Numeric Types and PackagesArithmetic LogicComparison and MultiplicationPartitioningSynthesis Process     Day 4, Module AdvSyn2Advanced ArithmeticArchitecting HardwareTxPort StatemachineFixed and Floating Point Types

Prerequisites

Students taking this course should have working knowledge of digital circuits and prior exposure to VHDL through experience or the course:

Other Recommended Courses

Students may also be interested in the following companion course:

Customization

Students taking this course should have working knowledge of digital circuits and prior exposure to VHDL through experience or the course:

Training Approach

This hands-on, how-to course is taught by experienced hardware designers using a computer driven projector. We prefer and encourage student and instructor interaction. Questions are welcome. Bring problematic code. 

Advanced VHDL Testbenches and Verification - OSVVM™ Boot Camp

Course Overview

Learn the latest VHDL verification methodologies for FPGA and ASIC design.   Techniques include transaction level modeling (tlm), self-checking, scoreboards, memory modeling, functional coverage, directed, algorithmic, constrained random, and intelligent testbench test generation.   Create a VHDL testbench environment that is competitive with other verification languages, such as SystemVerilog or 'e'.   Our methodolgies work on VHDL simulators without additional licenses and are accessible to RTL engineers.   

This course starts with simple testbenches and progressively increases the level of abstraction.   Along the way students learn about subprogram usage, libraries, file reading and writing, modeling issues, transaction-based testbenches, bus functional models, transaction level models (tlm), record types, resolution functions, abstractions for interface connectivity, model synchronization methods, protected types, access types (pointers), data structures (linked-lists, scoreboards, memories), directed, algorithmic, constrained random, and coverage driven random test generation, self-checking (result, timing, protocol checking and error injection), functional coverage, representation of analog values and periodic waveforms (such as triangle or sine waves), timing and execution of code, test planning, and configurations.   This class contains numerous examples that can be used as templates to accelerate your test and testbench development. 

The final result is a system-level, transaction-based, self-checking test environment.   Labs track with lecture giving students the opportunity to apply what they learn.   The techniques you learn in this class give VHDL a similar capability to other popular verification languages. 

What differentiates this class from other classes is that all of the techniques are implemented in VHDL and that core topics such as functional coverage, randomization, and data structures are covered in depth. 

Jumpstart your verification effort by reusing our packages for transaction level modeling (TLM), constrained random testing, functional coverage, Intelligent Coverage™ (coverage driven random - aka Intelligent Testbench) testing, scoreboards, and memories.

Intended Audience

Advanced VHDL Testbenches and Verification is recommended for experienced VHDL designers who are looking to improve their verification efficiency and effectiveness. 

Available Class Formats

This class is available online, at public venues, or on-site (at your location). 

Course Objectives

In this class, you will learn to:

  • Be more productive at design verification and testbenches
  • Create a transaction-based, system-level, self-checking test environment
  • Implement interface functionality with either a subprogram or bus functional model (aka transaction level model or tlm)
  • Use subprograms to abstract interface actions (CpuRead, CpuWrite, UartSend)
  • Write directed, algorithmic, constrained random, coverage driven random tests or a mixture of them.
  • Write a test plan that maximizes reuse from RTL to core to system level tests.
  • Reuse SynthWorks' packages for constrained random testing, functional coverage, memories, scoreboards, and interfaces.
  • Model interface behavior with proper timing
  • Model analog values and periodic waveforms
  • Effectively use VHDL's file read and write capabilities
  • Model RAM

Course Outline

   Day 1, Module Tb1Testbench OverviewBasic TestbenchesTransactions and SubprogramsModeling for VerificationVHDL IODay 2, Module Tb2Lab Review: Testing w/ subprogramsTransaction-Based Models (BFM)Elements of a Transaction-Based BFMData Structures for Verification Day 3, Module Tb3Lab Review: UartTx BFMCreating TestsConstrained Random TestingFunctional CoverageDay 4, Module Tb4Execution and TimingConfigurations and Simulation ManagementAdvanced CoverageAdvanced RandomizationDay 5, Module Tb4Lab Review: Scoreboards, Randomization, and CoverageModeling RAMTest PlansTransaction-Based BFM, Part 2

Prerequisites

Students taking this course should have prior exposure to VHDL through experience or the course:

Other Recommended Courses

Students may also be interested in either or both of the following companion courses:

Class Details

This class is a 5-day journey into VHDL coding styles, techniques, and methodologies that will help you become more productive at design verification and testbenches. 

The heart this approach is transaction-based testing. Transaction-based testing abstractly represents an the interface operation, such as a CPU read, CPU write, UART transmit or UART receive. In this class we learn two forms of transaction-based testbenches: a simple subprogram based approach, and a more capable bus functional model based approach. Both approaches use subprograms to initiate a transaction. A single test is a sequence of subprogram calls. A suite of tests is a collection of VHDL architectures. Using transaction calls makes tests easier to write and read, and more tests can be written in less time. The subprograms are created in a package, allowing them to be reused by all testbenches. Additional subprograms are used to encapsulate commonly used sequences of transactions (such as initialize UART and start DMA) further improving effectiveness of writing and reading tests. While either the subprogram implementation or the transaction model may change between subblock, core, and system-level tests, the subprogram call interface largely remains unchanged allowing many tests and test models to be reused or pre-used at each of these levels - further improving your efficiency. To simplify using records as an interface channel, SynthWorks provides a resolution package as open source. 

Another important topic is test generation. In class we learn how to create directed, algorithmic, constrained random, and coverage driven constrained random tests. Using these methods, students learn how create tests that model a CPU, UART, FIFO, memory, arithmetic, and analog designs. Since transactions are the basis for all of these tests, it is easy mix any of the techniques together. This means that if a directed or algorithmic sequence can achieve test coverage faster, it can be used either by itself or mixed in with the randomization methods. The randomization package that provides the foundation for constrained random verification is provided as open source. 

Since manually checking a test is tedious, error prone, and time consuming, making tests self-checking is important. In class we examine a number of different means of self-checking including result checking, protocol checking, timing checks, and error injection. The scoreboard data structure used in the class, and provided as a reusable package, is specifically focused toward result checking. 

Coverage tells us when a test is done. There are several forms of coverage including structural (code coverage) and functional. Structural or code coverage is coverage detected and reported by a simulator and is explored briefly in lecture and more detail in lab. Functional coverage goes beyond code coverage by looking for specific values or conditions to occur on an object or set of objects. We cover functional coverage in detail and facilitate implementing it with our open source coverage package. 

Design verification requires a good test plan. We learn to write test plans that reuse interface waveforms, bus functional models, and test cases at the RTL, core, and system levels. Reuse removes redundancy in the verification effort and reduces the amount of time the project takes. 

The SynthWorks testbench methodology uses the natural concurrency built into VHDL. Processes and models are used to create separate threads of execution for items that naturally run independently. When modeling statemachines in this approach, they can either be modeled concurrently, just like RTL code, or sequentially, just like software and OO approaches. To synchronize the separate processes, we use a synchronization primitive from a "library" of primitives contained in our open source utility package. The structure of the testbench is created with structural code just like RTL code. Compare this to other verification languages which rely on a complicated OO approach with "fork and join" to kludge in concurrency and methods for emulating elaboration and initialization that is already built into VHDL. 

Customization

All of SynthWorks' courses can be customized to meet your specific needs. 

Training Approach

This hands-on, how-to course is taught by experienced verification engineers. We prefer and encourage student and instructor interaction. Questions are welcome. Bring problematic code. 

Comprehensive VHDL Introduction

Course Overview

An in-depth introduction to VHDL and its application to design and verification of digital hardware (FPGAs and ASIC).   Provides a foundation in RTL and testbench coding styles needed by design and verification engineers who are new to VHDL.   Class comes with your choice of an Altera or Xilinx FPGA board to make sure you understand the whole process from simulation to chip.   

Through a series of lectures, exercises, and labs, students will gain a strong foundation in VHDL RTL and testbench coding techniques. Lectures contain numerous examples that show both syntax and coding style guidelines. Exercises provide immediate reinforcement of lecture materials. Labs give students hands-on experience writing RTL code, writing testbenches, running your simulator, running your synthesis tool, and programming the FPGA board. 

The comprehensive lecture guide provides an excellent after-class reference. Syntax and code that is not synthesizable is specifically noted. Labs account for approximately 50% of class time. Lab projects range from simple simulation and synthesis coding problems to small design projects. The design projects utilize all techniques learned in lecture and demonstrate how VHDL is used in a project environment. 

Intended Audience

Recommended as a first course in VHDL for design and verification engineers who need an in-depth understanding of VHDL and a solid foundation in RTL and testbench coding techniques. 

Prerequisites

None. Offered as a first course in VHDL. It is recommended that students are familiar with digital design. 

Available Class Formats

This class is available online, at public venues, or on-site (at your location). 

Course Objectives

Upon completion of this course, students will be able to:

  • Understand VHDL syntax and coding styles relevant to logic design
  • Write VHDL RTL hardware designs using good coding practices
  • Understand the synthesizable subset of VHDL
  • Understand problematic issues in coding hardware
  • Use types, overloading, and conversion functions from standard VHDL packages (std_logic_1164 and numeric_std)
  • Print messages in testbenches using TEXTIO
  • Write simple transaction-based testbenches using subprograms
  • Use your VHDL simulation and synthesis tools


Course Outline

Day 1

A Quick Introduction

Lab 1: Simple RTL and Testbench

Data TypesOperators

Concurrent Statements

Sequential Statements

Lab 2: Clock and Reset

Lab 3: RTL and Testbench


Day 2

RTL Essentials

Statemachine Coding Techniques

Lab4: RTL CodeData Objects

Designing with VHDL

Lab 5: Coding an FSM

Lab 6: Creating Hierarchy


Day 3

Testbench Essentials

Subprograms

Lab 7: Brute Force Testbenches

Testbenches and Timing

TextIO

Lab 8: Transaction-based Testbenches and TextIO

Lab 9: Synthesis and Programming an FPGA

    

Day 4

Numeric Types and Packages

RTL CodeVHDL Design Methodology

Lab 10: UART Transmit Data Path

Lab 11: UART Transmit Statemachine

Lab 12: Multiplier Accumulator

Take Home Labs

Digital Clock


Customization

All of SynthWorks' courses are modular and can be customized to meet your specific needs. 

Training Approach

This hands-on, how-to course is taught by experienced hardware designers using a computer driven projector. We prefer and encourage student and instructor interaction. Questions are welcome. Bring problematic code. 

Other Courses


SystemVerilog Testbench

Overview

In this three-day course, you will learn the key features and benefits of theSystemVerilog testbench language and its use in VCS. This course is a hands-onworkshop that reinforces the verification concepts taught in lecture through aseries of labs. At the end of this class, students should have the skills required towrite an object-oriented SystemVerilog testbench to verify a device under test withcoverage-driven constrained-random stimulus using VCS.To reinforce the lecture and accelerate mastery of the material, each student willcomplete a challenging test suite for real-world, system-based design.


Objectives

At the end of this workshop the student should be able to: 

• Build a SystemVerilog verification environment 

• Define testbench components using object-oriented programing. 

• Develop a stimulus generator to create constrained random test stimulus 

• Develop device driver routines to drive DUT input with stimulus fromgenerator 

• Develop device monitor routines to sample DUT output 

• Develop self-check routines to verify correctness of DUT output 

• Abstract DUT stimulus as data objects • Execute device drivers, monitors and self-checking routines concurrently 

• Communicate among concurrent routines using events, semaphores andmailboxesAudience Profile 

• Design or Verification engineers who write SystemVerilog testbenches at theblock or chip level.Prerequisites 

• To benefit the most from the material presented, students should have:o A basic understanding of Verilog HDLo Familiarity with UNIX workstations running X-windowso Familiarity with vi, emacs, or other UNIX text editors


Course Outline

Day 1 

• The Device Under Test 

• SystemVerilog Verification Environment 

• SystemVerilog Testbench Language Basics 

• Drive and Sample DUT Signals

Day 2 

• Concurrency 

• OOP: Encapsulation 

• OOP: Randomization

Day 3 

• OOP: Inheritance 

• Inter-Thread Communications 

• Functional Coverage 

• SV VMMSynopsys Tools Used 

• VCS

TCL for Synopsys Tool Scripting

Overview

This lecture focuses on TCL language for use within Synopsys implementation toolssuch as Design Compiler, IC Compiler and PrimeTime. It helps engineers juststarting out in EDA to learn how to write scripts for batch mode run including command syntax and using procedures to write re-usable scripts. It will also give anoverview about what TCL is and what areas to focus to get the most out of TCL as ascripting tool for EDA tools.


Objectives

At the end of this workshop the student should be able to:

• Write TCL scripts to execute in Synosys Design Compiler 

• Understand lists and collection

• Use regular expressions for search

• Use procedures for creating modular code segments

• Learn about attributes and how to use them in your scripts.


Who Should Attend

• Engineers working with DC/PT/ICC that required to write scripts for running the tools.

Prerequisites

To benefit the most from the material presented in this workshop, students should have:

• Experience with a high-level programming language (such as C) would bebeneficial

• Familiarity with UNIX workstations running X-windows

 • Familiarity with vi, EMACS or other UNIX text editor


Course Duration

This course will take approximately One (1) day to complete.


Course Content

• Introduction

• Data Types

• Procedures

• Control structures and operators

• Input & Output

• Regular expression

• Packages 

TCL Scripting

Overview

This lecture focuses on TCL language for use within Synopsys implementation toolssuch as Design Compiler, IC Compiler and PrimeTime. It helps engineers juststarting out in EDA to learn how to write scripts for batch mode run includingcommand syntax and using procedures to write re-usable scripts. It will also give anoverview about what TCL is and what areas to focus to get the most out of TCL as ascripting tool for EDA tools.

Objectives

At the end of this workshop the student should be able to:

• Write TCL scripts to execute in Synosys Design Compiler 

• Understand lists and collection

• Use regular expressions for search

• Use procedures for creating modular code segments

• Learn about attributes and how to use them in your scripts.


Who Should Attend

• Engineers working with DC/PT/ICC that required to write scripts for runningthe tools.

Prerequisites

To benefit the most from the material presented in this workshop, students shouldhave:

• Experience with a high-level programming language (such as C) would bebeneficial

• Familiarity with UNIX workstations running X-windows 

• Familiarity with vi, EMACS or other UNIX text editor

Course Duration

This course will take approximately One (1) day to complete.

Course Content

• Introduction

• Data Types

• Procedures

• Control structures and operators

• Input & Output

• Regular expression

• Packages 

Universal Verification Methodology

Synopsis

The need for a systematic approach towards verifying digital systems has given rise toadvanced testbench verification methodologies and frameworks such as OVM, UVM,OS-VVM, VMM, and AVM. This course introduces the key testbench concepts andverification framework of UVM, that allow engineers to systematically and accurately validate designs with minimal test cases. The course covers the simulation of digitalsystems and the design of proper testbenches for verification.


Course highlights

Participants will have practical design experience using the VCS-MX industry-standardlogic simulator from Synopsys.


What You Will Learn

This course concentrates on the theoretical and practical knowledge to allow participantsto achieve the following learning outcomes. Upon completing the course, participants would be able to:

● Simulate digital circuits with Synopsys’ VCS-MX.

● Learn and use SystemVerilog constructs for simulation and verification.

● Design constrained random testbenches

● Design tester components such as agents (drivers/generators, monitors, sequencers),checkers, and scoreboards using UVM techniques.

● Overview of transaction-level modelling (TLM), bus functional modelling (BFM),temporal assertions-based verification (ABV), and functional coverage.


Who Should Attend

This course is particularly suited for engineers involved in HDL-flow digital designsimulation, verification and testing. 


Prerequisites

Participants should have a diploma/degree in electronics (and related) engineering withan understanding of digital systems. Knowledge in VHDL/Verilog/SystemVerilog fordeveloping basic simulation testbenches is required.


Course Methodology

This course is presented in a workshop style with example-led lectures interlaced withdemonstrations and hands-on practical for maximum understanding.


Course Duration

Three days, 0900 to 1700.


Course Structure

1. Introduction 

  • Overview of UVMo 
  • Overview of Constrained Random Verification


2. Constrained Random Verificationo 

  • Test vector randomisationo
  • Benefits of randomisationo 
  • Benefits of UVM for constrained randomisation 


3. UVM Basicso 

  • Structure of UVM testbencho 
  • Execution Phaseso 
  • UVM Classes: Factories, transactions, sequences, drivers, agents,environments


4. UVM Reporting 

  • Reporting class
  • UVM reporting methods
  •  Actionso Verbosity and severity levelso 
  • Configuration functions


5. Overview of TLM and BFM

  • Advantages of TLMo UVM TLM2 Interfaces
  • TLM2 Sockets
Verification with VCS

Duration: 1 day

Introduction: 

VCS is a HDL Simulator from Synopsys. This coursei ntroduces participants to Verilog HDL designverification using Synopsys VCS simulator. The course covers debugging techniques and improving verification performance.


Who Should Attend: 

Verification Engineers working HDL designs


Training Outcome: 

On completion of training, participants will be able to:

• Compile Verilog designs using VCS

• Simulate Verilog designs using VCS

• Debug Verilog source code errors using VCS

• Improve simulation performanceHow ParticipantsWill Learn:This program will be delivered via lectures, discussions and hands-on lab.


Program Schedule: 

• VCS Simulation Basics

• VCS Debugging Basics

• Discovery Visual Environment

• Post-Processing with VCD+Files

• Gate-level Verification

• Tool Optimization

Verilog HDL

Duration: 3 days

Introduction: 

This three-day workshop introduces the student to the Verilog®language with a focus on technique for doing Register TransferLevel (RTL) modeling. VCS tips and techniques for optimal use arecovered along with VCS usage for labs. This course is mixed lectureand exercises, with an exercise for nearly every topic. Largespectrum of the language is covered with emphasis on RTLmodeling, procedural assignments, scheduling and event queriesalong with discussion on Synopsys synthesis, VCS and modelingstate machines.


Who Should Attend: 

IC Design Engineers


Training Outcome: 

On completion of training, participants will be able to:

• Demonstrate an applied, working knowledge of Verilog language constructs 

• Demonstrate an understanding of procedural eventscheduling and show the use of blocking and nonblockingstatements 

• Write general Verilog models 

• Simulate and debug Verilog models using VCS• Write combinational Verilog circuit descriptions usingmultiple styles and methods

• Write synthesizable RTL models and then synthesizethem into gate level models

• Write test-benches and verify Verilog models

• Write models with bi-directional ports and tri-statebuses

• Write synthesizable state machinesHow ParticipantsWill Learn:This program will be delivered via lectures, discussionsand hands-on lab.  

Contents:

• Lexical Conventions 

• Module anatomy 

• Port declarations 

• Module instances 

• Data types 

• Nets, registers, parameter 

• Procedural blocks 

• Timing • controls, event queue 

• Blocking/Non blocking Proc. 

• Operators 

• Programming statements 

• Task & Functions 

• Verilog for Test 

• X & Tri-State Buffers 

• Gate-level Modeling 

• Finite State machines

Fundamentals of Digital Signal Processing (DSP)

Synopsis

Digital signal processing (DSP) is the backbone of numerous technological fields, such as wired andwireless communication, military and intelligence gathering, industrial process control, medicalscience, cryptography and transportation, just to name a few. DSP algorithms such as spectralanalysis and Kalman filtering -- traditionally executed with specialised digital signal processors -- arenow increasingly carried out with FPGAs for their greater processing capabilities, increased chip-level integration and lower power consumption. The move towards FPGAs also mean DSP algorithms arenow "coded" in hardware description languages rather than assembly, C, or C++.This course concentrates on DSP theory, with a heavy emphasis on mathematical modelling. To ease understanding, simple practical exercises on a few key mathematical fundamentals of DSP systemswill also be carried out.Course highlightsParticipants will have practical design experience using mathematical modelling tools (e.g. Sage orMatlab).


What You Will Learn

This course concentrates on the theoretical and practical knowledge to allow participants to achievethe following learning outcomes. Upon completing the course, participants would be able to:

  • Understand the theory and mathematics behind signal processing systems.
  •  Model DSP systems using Sage or Matlab.


Who Should Attend

This course is particularly suitable as an introductory-level course in digital signal processing (DSP)for engineers and scientists.


Prerequisites

Participants should have a diploma/degree in electronics (and related) engineering with an understanding of digital systems. Working knowledge on DSP theory is encouraged, but not required.


Course Methodology

This course is presented in a workshop style with example-led lectures interlaced with demonstrations and hands-on practical for maximum understanding.


Course Duration

Three (3) days, 0900 to 1700.


Course Structure

1. Introduction

  • Overview of digital signal processing.
  • Discrete-time vs. continuous-time: Analogies and similarities.


2. Applications of DSP

  • Digital filtering and equalisation.
  • Source coding: data compression, encryption, scrambling.
  • Image/video processing, audio/speech processing.
  • Digital communications systems.
  • Digital control systems.


3. DSP fundamentals

  • Discrete-time (DT) vs. continuous-time (CT) systems and notations.
  • Difference equations. Convolution sum: A widely-used concept for DSP designs.
  • The unit impulse excitation and response for determining system characteristics.
  •  Concept of convolution.
  • Similarities between the DT convolution sum and the CT convolution integral.
  •  Responses of systems to other standard impulse excitations.
  •  The Fourier series.
  •  Time-to-frequency transformations: the Laplace, Fourier, and z transforms.
  • The Laplace transform.
  • The Fourier transform.
  • The discrete Fourier transform (DFT).
  • The fast Fourier transform (FFT): a popular DFT algorithm.
  • Hands-on Practical 1: Modelling the FFT algorithm.
  • The z-transform.
  • Similarities between the DT z-transform, and the CT transforms such as Laplace (s-domain)and Fourier transforms.

4. Correlation, energy spectral density, power spectral density

  •  The correlation function.
  •  Autocorrelation.
  •  Cross correlation.
  •  Similarities and differences between correlation functions and convolution.
  •  Energy spectral density (ESD).
  •  Power spectral density (PSD).
  •  Relation of ESD and PSD to autocorrelation.

5. Digital filter design techniques

  •  Revision of analogue (CT) filters: Butterworth, Chebyshev, and Bessel.
  •  Overview of digital filter design techniques: bilinear transform, matched z-transform,impulse invariance, step invariance, difference equation approximation.
  •  Infinite-impulse-response (IIR) versus finite-impulse-response (FIR) filters.6. Infinite impulse response filters Overview of infinite impulse response (IIR) filters. Bilinear transformation. Hands-on Practical 2: Modelling a DT Butterworth IIR filter using the bilineartransformation.
  •  Matched z-transform.
  •  Hands-on Practical 3: Modelling a DT Chebyshev IIR filter using the matched z-transform.
  •  Impulse-invariant and step-invariant design techniques.
  •  Hands-on Practical 4: Modelling a DT Chebyshev IIR filter using the impulse-invarianttechnique.
  •  Frequency transformation - high-pass, band-pass, band-stop.7. Finite impulse response filters
  •  Overview of finite impulse response (FIR) filters. Finite-duration impulse responses: truncation of infinite-duration impulse responses.
  •  A simple finite impulse response (FIR) filter: the averaging filter.
  •  Hands-on Practical 5: Modelling an averaging filter.
  •  FIR filter design: deriving filter coefficients from a given filter specification.
  •  Windowing method.
  •  Parks-McClellan method.
  •  Hands-on Practical 6: Modelling of a parameterisable FIR filter.8. Adaptive equalisation/filtering
  •  Overview of estimation theory Maximum-likelihood (ML) estimators.
  •  Hands-on Practical 7: Modelling an adaptive channel estimator using ML sequencedetection.
  •  Adaptive linear equalisers 
  •  Zero-forcing equaliser.
  • Least-mean-square (LMS) equaliser: Mean-square-error minimisation.
  • Wiener equaliser / filter.
  • Hands-on Practical 8: Modelling a Wiener equaliser.
  •  Adaptive decision-feedback equaliser (DFE).
  •  Hands-on Practical 9: Modelling an adaptive DFE.
  •  Recursive least-squares (RLS) algorithms for adaptive equalisation Kalman equaliser / filter (Kalman algorithm).
  • Lattice filter (linear prediction algorithm).
  •  Hands-on Practical 10: Modelling a Kalman equaliser.
  •  Blind equalisers.9. [Optional]: Advanced topics.
  • 2-D convolution.
  •  2-D FIR: spatial filtering.
  •  Median filtering.
  •  2-D DFT and 2-D FFT.
Transaction-level Modelling (TLM) and Bus Functional Modelling (BFM) with VHDL

Synopsis

As systems-on-chips (SoC) integrate increasingly more features on a chip, the sheer complexitydemands a shift in design paradigm. With multiple inter-module routing groups within an SoC, it is nolonger feasible for bus interfaces to be designed using conventional low-level signallingmethodologies.We introduce the concept of transaction-level modelling (TLM) and bus functional modelling (BFM) inthis course, which are methods to encapsulate low-level signalling into high-level transactions.TLMs/BFMs simplify your testbenches and system-level designs by separating the low-level busmodels (BFMs) from the higher-level transactor abstractions (TLMs), making your testbenches/SoCdesigns easier to manage and maintain. These concepts are very useful for both simulationtestbenches as well as synthesisable SoC bus interface designs.Participants will have an in-depth understanding of TLMs and BFMs, and will design transactors andbus functional models for a simple FIFO application, commonly found in numerous real-worldapplications. We demonstrate how modules could easily communicate with one another via a businterface designed using TLM and BFM techniques. Communicating between two individualtestbench/SoC components is as simple as making a procedure-call statement.


Course highlights

Participants will have practical design experience using industry-standard logic simulators (e.g.Mentor Graphics QuestaSim, or Synopsys VCS-MX), logic synthesis tools (e.g. Synopsys DesignCompiler, or Xilinx Vivado), and development boards with Xilinx Zynq or Altera Cyclone V FPGAs.


What You Will Learn

This course concentrates on the theoretical and practical knowledge to allow participants to achievethe following learning outcomes. Upon completing the course, participants would be able to: Develop and implement TLM and BFM techniques in bus protocol designs. Design and simulate transactors and BFMs. Synthesise and verify transactors and BFMs.


Who Should Attend

This course is particularly suited for engineers involved in ARM-based system-on-chip designs,verification and testing.


Prerequisites

Participants should have a diploma/degree in electronics (and related) engineering with anunderstanding of digital systems. They must be familiar with VHDL/Verilog for developingsynthesisable digital systems or simulation testbenches. Participants are strongly encouraged toattend the following course(s) prior to attending this course: VHDL Subprograms for Synthesis and Simulations

Course Methodology

This course is presented in a workshop style with example-led lectures interlaced with demonstrationsand hands-on practical for maximum understanding. 


Course Duration

Three (3) days, 0900 to 1700.


Course Structure

1. Introduction

  •  Overview of testbenches and systems-on-chip (SoC) architectures.
  • Overview of bus architecture designs. Overview of transaction-level modelling (TLM).
  • Overview of bus functional modelling (BFM). Overview of available VHDL TLM/BFM frameworks.

2. Transactor design

  • Concept of transactions.
  • Concept of TLM and its applications.
  • Review of VHDL procedures.
  • Typical example of a transaction-level model (transactor).
  • Generic design for transactors.
  • Hands-on Practical 1: Designing a FIFO master transactor.

3. Bus functional model design

  • Concept of bus functional models (BFM).
  • Revision on finite-state machines (FSM).
  • Typical example of a BFM.
  • Encapsulating low-level protocol signalling using a BFM.
  • Hands-on Practical 2: BFM design of the FIFO Master using non-synthesisable VHDL.
  •  Hands-on Practical 3: BFM design of the FIFO Master using synthesisable VHDL.

4. Transactor and BFM simulation

  • Simulation requirements and setup.
  • Hands-on Practical 4: Simulating the FIFO Master TLM/BFM models.

5. Transactor and BFM synthesis and implementation

  • Configuring tools for synthesis.
  • Hands-on Practical 5: Synthesising the FIFO Master TLM and BFM.
  • Automatic-placement and routing (APR), design partitioning, and design assembly.
  • Configuring tools for APR and design assembly.
  •  Hands-on Practical 6: Implementing the FIFO Master TLM/BFM design.

6. Transactor and BFM hardware verification

  • Hardware verification flow for post-silicon verification.
  • Overview of the development board, clock and reset assignments, JTAG set-up.
  • Configuring tools for verification.
  • Hands-on Practical 7: Verifying the FIFO TLM/BFM design on hardware.

7. Optimisation for Area and Power

  • RTL optimisation techniques.
  • Specifying area constraints, floorplanning, and design partitioning.
  • Configuring and using area and power optimisation tools.
  • Hands-on Practical 8: Optimising the design for area and power.

8. Speed Optimisation Techniques

  • Manual placement techniques for high-performance design.
  • Concept of timing closure.
  • Specifying timing constraints.
  • Static timing analysis (STA).
  • Configuring and using speed optimisation tools.
  • Hands-on Practical 9: Optimising for speed.
VHDL Simulations and Testbenches

Synopsis

The ubiquity and complexity of commercial, professional and industrial digital systems has beenincreasing exponentially over the years as we integrate more and more features into these systems.Coupled with the ever shortening time-to-market and the proliferation of systems in safety criticalareas, the immense challenges of engineers are to ensure their complex designs are error free andconform to the desired functionality. These challenges has made verification, especially at the presiliconstage, a vital stage in the design process.

The need for a systematic approach towards verifying digital systems has given rise to advancedtestbench verification methodologies such as OS-VVM, OVM, UVM and AVM. This course introducesthe key testbench concepts and verification framework of OS-VVM, that allow engineers tosystematically and accurately validate designs with minimal test cases. The course covers thesimulation of digital systems and the design of proper testbenches for verification. Ultimately, thiscourse aims to arm engineers with a powerful tool to ensure their designs can be properly tested in atimely manner. 


Course highlights

Participants will have practical design experience using industry-standard logic simulators (e.g.Synopsys VCS-MX or Mentor Graphics QuestaSim/ModelSim). 


What You Will Learn

This course concentrates on the theoretical and practical knowledge to allow participants to achievethe following learning outcomes. Upon completing the course, participants would be able to:

  • Simulate digital circuits with Synopsys’ VCS-MX or Mentor Graphics ModelSim.
  • Learn and use VHDL constructs for simulation and verification.
  • Design tester components such as stimuli / test vector generators, transaction monitors,response checkers, and scoreboards.
  • Design testbench components using techniques such as simple assertions, file I/O, andconstrained random verification (CRV).
  • Have an overview of advanced techniques such as transaction-level modelling (TLM), busfunctional modelling (BFM), temporal assertions-based verification (ABV), constrained randomverification (CRV), and functional coverage


Who Should Attend

This course is particularly suited for engineers involved in HDL-flow digital design simulation,verification and testing.


Prerequisites

Participants should have a diploma/degree in electronics (and related) engineering with anunderstanding of digital systems. Knowledge in VHDL/Verilog for developing synthesizable digital systems or simulation testbenches is helpful but not required. 


Course Methodology

This course is presented in a workshop style with example-led lectures interlaced with demonstrations and hands-on practical for maximum understanding.


Course Duration

Three days, 0900 to 1700. 


Course Structure

1. Introduction

  • IC/FPGA design and verification flow.
  • The Design Under Verification (DUV).
  • Overview of testbench components.

2. Stimuli vector generator design

  • Concept of test vector generation, types of stimuli (directed, pseudorandom).
  • Unconstrained vs. constrained randomisation.
  • Unconstrained randomisation of stimuli.
  • Hands-on Practical 1: Unconstrained random stimuli vector generator design andsimulation.
  • Constrained random verification (CRV).
  • Hands-on Practical 2: Constrained random stimuli vector generator design and simulation.
  • File I/O (input only).
  • Hands-on Practical 3: Reading stimuli from a file.

3. Transaction monitor design

  • Concept of transaction monitoring.
  • Simple (non-temporal) assertions-based verification (ABV).
  • Hands-on Practical 4: Transaction monitor design using non-temporal assertions.

4. Response checker design

  • Concept of response checking.
  • Scoreboards.
  • Hands-on Practical 5: Response checker design using scoreboards logged to simulator’sconsole.
  • File I/O (output only).
  • Hands-on Practical 6: Response checker design using scoreboards logged to a file.

5. Overview of advanced testbench techniques

  • Temporal assertions-based verification (ABV) with Property Specification Language (PSL).
  • Functional coverage: an introduction to OS-VVM's intelligent coverage-driven constrainedrandomisation.
  • Transaction-level modelling (TLM) and bus functional modelling (BFM).
Training Programmes